A so-called system on chip, or system on a chip, typically abbreviated SoC, is an integrated circuit (IC) that integrates all components of an electronic system into a single chip. The components comprised in the SoC in this way form an operational system that may replace an arrangement of a plurality of separate components.
The SoC may comprise one or more digital signal processors, also called cores or central processing units that are capable of executing sequences of instructions to process digital data. Accordingly the SoC may comprise memory for storing digital information, wherein the memory may be volatile or non-volatile and wherein the digital information may comprise code executable by a digital signal processor. To enable access to the memory the comprised cores may be communicatively coupled to the memory, for example, by a bus system, which may couple to further comprised components. Furthermore the SoC may comprise a power supply that provides supply voltages for the comprised components and a timing unit that provides a clock signal for components. Also the SoC may comprise at least one interface for communicatively coupling the SoC to another system for information exchange, wherein the at least one interface may be analogue or digital.
The SoC typically exhibits a plurality of pins for supplying power to the SoC and connecting to peripheral systems, wherein the pins may be arbitrarily implemented, i.e. for example as a ball grid array.
In order to enable to set the system into a defined condition the system provides a so-called reset function, which can be triggered by various events. The reset function can be implemented as a software command to be provided via a communication line. Alternatively one or more of the pins are so-called reset-pins. Upon application of a predefined signal, i.e. typically a voltage level, the system can be set to a predefined condition, wherein the reset action typically stops all processing actions performed in and by the SoC.
While a reset event can be triggered as part of starting the system, i.e. to bring the system into a predefined condition when initially powering up the system, reset events may also occur while the system has been running for a while.
This sudden stop of all processing actions may cause problems, particularly when the reset signal is applied not as part of a startup sequence but during normal operation of the SoC.
If system context, i.e. information reflecting the current processing context of the SoC, or trace information, i.e. information reflecting currently processed information, is stored into memory, i.e. particularly into memory comprised in the SoC itself, then this data may be corrupted by the reset event since the system might stop operating when performing the steps of writing the information. Even if the reset event/signal occurs synchronous with a clock signal it is possible that a write action may be corrupted since the write action may span several clock cycles for writing a data block. Thus that data block may be stored incomplete, i.e. corrupted. In case the system is subsequently fully restarted, i.e. any data written during a previous operation are ignored, then this problem is of minor importance. However, in case the SoC takes the incompletely stored data into account upon restart, for example in order to accelerate the restart process and to restore the previous operational context, then these final data writes may be significant.
Another problem may arise in case there are multiple simultaneous data writes in progress to different memories, i.e. different and non-synchronized memory entities. In that case it is desirable that the stored data is consistent and coherent across these memories. For example, if a so-called debug-trace is running, i.e. runtime data reflecting the instruction trace information and the processed in- and output data are stored to memory for monitoring the operation of the SoC, then it is also desirable that any store operations, which have been traced, can be matched to real write data in the memory. In case of an unexpected reset event, which abruptly stops all activities of the SoC, these data may be stored inconsistent and corrupted thus leaving the latest operations being untraced.
Another problem can arise from the power supply components comprised in the SoC. If the SoC is powered from a voltage regulator, which typically is the case, then the regulator will see a sudden rapid stop in load when a reset event triggers all components to immediately stop operating. This sudden drop of electric load in the supply circuitry can cause an voltage overshoot or voltage spike which in turn may cause malfunction or even damage at the time of reset or restart. This problem could be handled by a more flexible and stable voltage regulator, wherein a typical solution requires usage of a larger capacitance for smoothing the output voltage, but wherein a larger capacitance, i.e. a larger analogue component, is not desirable and costly in a system implemented on a single chip.